Eecs 312 Section 5 3 Section 5.3 – the bjt as an amp and switch. Discussion session 3: help with diodes and power consumption. notes. discussion session 4: help with lab 2. no slides. discussion session 5: mosfet models and layouts. notes. discussion session 6: mosfet models and sizing. notes. discussion session 7: logical effort. notes. discussion session 8: help with lab 3. no slides. discussion session 9.
Eecs 312 Section 11 3 Course web page for eecs 312. Assignments lab 3 due lab 4 out lab 4 video takeaways arrive 10 minutes early with your approved notes sheet and photo id. exam covers content through domino logic. Chapter 5 bipolar junction transistors. bjt structure and mode of operation. As you read through your notes, text, examples, handouts, etc., you will frequently run into a line, paragraph, or entire section that you don’t understand. do you skip over it, or work at it till you understand?.
Eecs 312 Section 5 2 Chapter 5 bipolar junction transistors. bjt structure and mode of operation. As you read through your notes, text, examples, handouts, etc., you will frequently run into a line, paragraph, or entire section that you don’t understand. do you skip over it, or work at it till you understand?. Problem 10: this is an extension from lab assignment 1 and what we learned about pmosfets in lectures 2 and 3. problems 11 and 12: we learned these in lecture 4. Midterm exam may cover anything up to and including 3 october. make sure you did the assigned reading. look though all the on line slides for anything surprising. review lab and homework assignments. if you want to study with other students, please use mailing list to nd partners. Section 10.3 cmos logic gate circuits section 10.4 pseudo nmos logic gate circuits. Homework due at the beginning of lecture. 5% penalty if late on same day. 10% penalty per day for late assignments. no credit after assignment covered in class or discussion session. penalty is gradual – avoid all nighters. the goal is competence, not exhaustion.
Eecs 312 Section 3 6 Problem 10: this is an extension from lab assignment 1 and what we learned about pmosfets in lectures 2 and 3. problems 11 and 12: we learned these in lecture 4. Midterm exam may cover anything up to and including 3 october. make sure you did the assigned reading. look though all the on line slides for anything surprising. review lab and homework assignments. if you want to study with other students, please use mailing list to nd partners. Section 10.3 cmos logic gate circuits section 10.4 pseudo nmos logic gate circuits. Homework due at the beginning of lecture. 5% penalty if late on same day. 10% penalty per day for late assignments. no credit after assignment covered in class or discussion session. penalty is gradual – avoid all nighters. the goal is competence, not exhaustion.
Eecs 312 Section 3 3 Section 10.3 cmos logic gate circuits section 10.4 pseudo nmos logic gate circuits. Homework due at the beginning of lecture. 5% penalty if late on same day. 10% penalty per day for late assignments. no credit after assignment covered in class or discussion session. penalty is gradual – avoid all nighters. the goal is competence, not exhaustion.
Eecs 312 Section 3 2
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