Adarsh K S Adarsh Threads Say More ๐ hi, iโm @adarshprakash789 ๐ iโm interested in vlsi design & verification, rtl to gdsii flow, ai ml on edge devices, and building silicon proven socs. ๐ฑ iโm currently learning advanced asic verification using systemverilog uvm and exploring physical design optimization techniques using synopsys tools. Whether it's crafting elegant code or bringing ideas to life online, i am committed to continuous learning and growth in the dynamic field of computer science. i have made various projects in various languages and have uploaded them on github. you can check all my projects by clicking here.
Adarsh 1001 Github Contribute to adarshprakash789 adarshprakash789 development by creating an account on github. Developed using java and mysql for managing library records efficiently. built with node.js and socket.io for real time messaging. curiosity drives me to keep exploring, learning, and improving every day. Develop a reusable, scalable uvm based verification environment supporting heterogeneous soc components (arm, risc v, dsps). adarshprakash789 universal verification platform for heterogeneous socs uvp hs. This project focuses on designing a scalable, reusable verification framework using systemverilog and uvm to verify complex processor architectures. the aim is to create a robust environment with advanced testbenches and coverage metrics for comprehensive validation of new features.
Adarsh8469 Github Develop a reusable, scalable uvm based verification environment supporting heterogeneous soc components (arm, risc v, dsps). adarshprakash789 universal verification platform for heterogeneous socs uvp hs. This project focuses on designing a scalable, reusable verification framework using systemverilog and uvm to verify complex processor architectures. the aim is to create a robust environment with advanced testbenches and coverage metrics for comprehensive validation of new features. This project demonstrates a power aware verification flow for a low power asic design using synopsys tools (vcs and primetime px) along with uvm based systemverilog testbenches. power aware verification for low power asic design license at main ยท adarshprakash789 power aware verification for low power asic design. Learn more about blocking users. add an optional note maximum 250 characters. please don't include any personal information such as legal names or email addresses. markdown supported. this note will be visible to only you. contact github support about this userโs behavior. learn more about reporting abuse. Asic verification engineer | proficient in uvm, systemverilog, and rtl design verification | b.tech in ece | expertise in functional verification adarshprakash789. This project showcases a universal verification methodology (uvm) based verification framework for a system on chip (soc) design comprising multiple subsystems including cpu, dma, memory, and peripheral interfaces such as i2c, spi, and amba. the focus was to establish a modular and reusable testbench architecture that ensures seamless integration.
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